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VV6501
VGA CMOS Color Image Sensor
Features
s 640 x 480 VGA resolution s 1/4 inch format lens compatible s On board 10 bit ADC s On board voltage regulators s Automatic dark calibration s On board audio amplifier s I2C interface s Low power suspend mode s 4 or 5 wire nibble output s Framegrabber signals: QCK and FST
Technical Specifications
Image Size Pixel size Array size Analogue gain Sensitivity (typ.) Maximum frame rate Supply voltage 640 x 480 (VGA) 5.6 m x 5.6 m 3.6 mm x 2.7 mm x1 to x16 2.05 V/lux-sec 30 fps (with 24MHz clock) 5V (USB) 3V3 direct drive Power consumption Active (30fps) Suspend < 30 mA < 100 A 0oC - 40oC 36 pin CLCC
Description
This image sensor based on STMicroelectronics CMOS technology is Bayer colorised. The sensor provides a raw digital video output which also contains embedded codes to facilitate external synchronisation. The sensor interfaces to a range of STMicroelectronics companion processors for applications such as USB webcams and digital stills cameras. An I2C interface allows an external processor to configure the device and control exposure and gain settings. A low-power pin-driven suspend mode simplifies USB-based designs. On board voltage regulators operate from a 5V USB supply and generate 3V3 and 1V8 power supplies for external processors.
Operating temperature Package type
Ordering Details
Part Number
VV6501C001
Description
36pin CLCC, colorised sensor
September 2003
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VV6501
Table of Contents
Chapter 1
1.1 1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Sensor overview ................................................................................................................... 4 Typical application ................................................................................................................ 5
Chapter 2
2.1 2.2
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin position ........................................................................................................................... 6 Pin description ...................................................................................................................... 7
Chapter 3
3.1 3.2 3.3 3.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Video block ........................................................................................................................... 9 Audio block ......................................................................................................................... 22 Power management ........................................................................................................... 24 Device operating modes .................................................................................................... 26
Chapter 4
4.1 4.2 4.3
Serial Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
General description ............................................................................................................ 28 Serial communication protocol ........................................................................................... 28 Types of messages ............................................................................................................ 30
Chapter 5
5.1 5.2
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Register map ...................................................................................................................... 32 Register description ........................................................................................................... 34
Chapter 6
6.1 6.2 6.3 6.4 6.5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Absolute maximum ratings ................................................................................................. 43 Operating conditions .......................................................................................................... 43 Thermal data ...................................................................................................................... 43 DC electrical characteristics ............................................................................................... 44 AC electrical characteristics ............................................................................................... 47
Chapter 7
7.1 7.2 7.3 7.4
Optical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Optical characterisation methods ....................................................................................... 48 Optical characterisation results .......................................................................................... 49 Spectral response .............................................................................................................. 50 Blooming ............................................................................................................................ 50
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VV6501 Chapter 8
8.1 8.2 8.3 8.4 8.5 8.6
Defect Categorisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction ........................................................................................................................ 51 Pixel defects ....................................................................................................................... 51 Sensor array area definition ............................................................................................... 52 Pixel fault definitions .......................................................................................................... 53 Summary pass criteria ....................................................................................................... 54 Physical aberrations ........................................................................................................... 55
Chapter 9 Chapter 10
10.1 10.2 10.3
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Design-In Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Basic support circuit ........................................................................................................... 58 Transistor choice ................................................................................................................ 58 Pin 1 and image orientation ............................................................................................... 58
Chapter 11
Evaluation Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
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Overview
VV6501
1
1.1
Overview
Sensor overview
The VV6501 VGA image sensor produces raw digital video data at up to 30 frames per second. The image data is digitised using an internal 10-bit column ADC. The resulting 10-bit output data includes embedded codes for synchronization. The data is formatted as 5-bit nibbles. A separate data qualification clock (qck) and frame start (fst) signals are also provided. The sensor is fully configurable using an I 2C interface. The sensor also contains an audio low-noise preamplifier for use with an external microphone. The sensor is optimized for USB applications and contains voltage regulators which drive external pass transistors to produce 3V3 and 1V8 supplies. These supplies may be used by external processors. A dedicated SUSPEND input pin may be used to force the device into a low power state while maintaining the device configuration. A power-on reset signal (PORB) may be used to reset external devices. Figure 1: VV6501 block diagram
PDVREG1V8
VBASE1V8
VBASE3V3
VBG
V5V
VIDEOVSS
VDIG1V8
VDIG3V3
VIDEO3V3
NC
1V8 digital regulator
GNDS VDD PORB SUSPEND TEST
3V3 digital regulator
Video regulator
Audio regulator
NC
VIDEO3V3
AUD3V3
AUD3V3 AUDOUTP
Digital interface
Analog video block
Audio amplifier
MICIN MICBIAS
VDD GND
AUDOUTN AUDREF
10-bit video data
AUDVSS
SCL SDA CLKIN
FST QCLK
D0
D1
GND D2
D3
D4
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VV6501
Overview
1.2
1.2.1
Typical application
USB webcam
This sensor may be used in conjunction with the STMicroelectronics STV0676 co-processor to produce a low cost USB webcam. In this application the co-processor supplies the sensor clock and uses the embedded control sequences to synchronise with the frame and line level timings. It then performs the colour processing on the raw image data from the sensor before supplying the final image data to the host using the USB interface. The voltage regulators on-board the sensor are used to control external bipolar transistors to derive the supplies for the sensor and co-processor from the 5V USB supply. This approach eliminates the requirement for more costly external voltage regulation circuitry.
Figure 2 below illustrates a typical system using VV6501.
Figure 2: USB camera system using STV0676
USB Webcam
V5V GND VV6501
Power management Digital interface
3V3 1V8
I2C
STV0676 Co-processor
suspend video D[4:0]
USB Hub
USB-power USB - data
USB Connector
Video processing
VGA pixel array
Microphone
Audio amplifier
USB interface
The input USB supply is 5 V. The 3V3 digital regulator generates the supply for the sensor digital part and the co-processor IOs. The 1V8 regulator generates the core supply for the co-processor.
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Device Pinout
VV6501
2
2.1
Device Pinout
Pin position
Figure 3: Pin position
PDVREG1V8
VBASE1V8
VBASE3V3
VIDEOVSS 34
5 GNDS PORB SUSPEND GND VDD GND SDA SCL CLKIN 6 7 8 9 10 11 12 13 14 15
4
3
2
1
36
35
33 32 31 30 29 28 27 26 25 24 NC NC AUD3V3 AUDOUTP MICIN MICBIAS AUDOUTN AUDREF AUDVSS
16
17
18
19
20
21
22
23
GND
FST
D0
D1
D2
D3
QCLK
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VDD
D4
VIDEO3V3
VDIG1V8
VDIG3V3
VBG
V5V
VV6501
Device Pinout
2.2
Pin description
Table 1: Pin description
Pin Number
Digital regulators
Pin Name
Pin Type
Description
1 2 3 4
VBASE3V3 VDIG3V3 VBASE1V8 VDIG1V8
PWR PWR PWR PWR
3.3 V digital regulator (connect to external PNP base) 3.3 V digital regulator (connect to external PNP collector) 1.8 V digital regulator (connect to external PNP base) 1.8 V digital regulator (connect to external PNP collector)
Digital inputs/outputs
5
PDVREG1V8
PWR
1.8 V reg power down signal 1 - Regulator powered down 0 - Regulator powered up Connect to GND Power on reset signal (active low) Sensor suspend input signal (active high) with Schmitt buffer Input pin with Schmitt buffer. Connect to GND Digital IO supply 3.3 V Digital ground Bidirectional I2C pin Bidirectional I2C pin. I2C clock line Input clock pin with Schmitt buffer FST signal (active high). 2 mA output pad Sensor data qualifying clock. 4 mA output pad D0 signal (data bus, bit 0). 4 mA output pad D1 signal (data bus, bit 1). 4 mA output pad Digital IO supply 3.3V Digital IO/core source ground D2 signal (data bus, bit 2). 4 mA output pad D3 signal (data bus, bit 3). 4 mA output pad D4 signal (data bus, bit 4). 4 mA output pad
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
GNDS PORB SUSPEND TEST VDD GND SDA SCL CLKIN FST QCLK D0 D1 VDD GND D2 D3 D4
PWR O I I PWR PWR IO IO I O O O O PWR PWR O O O
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Device Pinout
Table 1: Pin description
Pin Number
Audio amplifier
VV6501
Pin Name
Pin Type
Description
24 25 26 27 28 29 30
Video regulator
AUDVSS AUDREF AUDOUTN MICBIAS MICIN AUDOUTP AUD3V3
PWR PWR O PWR I O PWR
Audio ground Audio reference voltage (requires external decoupling capacitor) Audio negative output Audio microphone bias voltage Audio microphone input signal Audio positive output 3.3 V audio analogue supply (requires external decoupling capacitor)
33 34 35 36
Not connected
VIDEO3V3 VIDEOVSS VBG V5V
PWR PWR PWR PWR
Analogue video 3.3 V Analogue video ground 5 V BandGap voltage (requires external decoupling capacitor) USB power supply (4 - 5.5 V)
31,32
-
-
Not connected
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VV6501
Functional Description
3
Functional Description
The first three sections of this chapter detail the main blocks in the device:
q q q
Video Audio Power management
The final section describes the device level operating modes including suspend.
3.1
3.1.1
Video block
Overview
The analog core of the video block contains a VGA sized pixel array. The integration time and access for a row of pixels is controlled by the Y-address block. The row of pixels being read is converted using a 10-bit in-column ADC. The digitised data is readout into the digital block for formatting. The 10-b data is transferred to the co-processor over a 5-wire digital bus as two 5-b nibbles. The exposure or integration time for the pixel array is calculated by the external co-processor and delivered to the sensor using the I2C interface. Figure 4: Overview of video block
SRAM line store X-Address Column ADC
10-b image data Readout structure
Timing & control Digital logic VGA photodiode array
10-b image data D[4:0] Coprocessor I2C FST, QCK
Y address
Data synchronization can be achieved either by using the embedded codes within the data stream or by making use of the dedicated FST and QCK pins.
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Functional Description 3.1.2 Imaging array
The physical pixel array is 656 x 496 pixels. The pixel size is 5.6 m by 5.6 m. Figure 5: Pixel array
2 border rows
VV6501
2 border columns
Visible array (640 x 480) 5.6 m x 5.6 m pixel (3.5840 mm x 2.6880 mm)
2 border columns
2 border rows
640 pixels 644 pixels
The additional border columns and rows are included to enable complete color reconstruction of the final 640 by 480 sized array.
Microlens
Microlenses placed above the visible pixels improve light gathering capability hence improving sensitivity.
3.1.3
Sensor data overview
Sensor data is output on a 5-wire bus. As well as pixel data there are embedded codes at the start and end of every video line. These codes are always preceded by an escape sequence which is guaranteed not to appear in the video data itself. Table 2: Video data values
Read-out order Form of encoding
Progressive scan (non-interlaced) Uniformly quantized, PCM, 8/10 bits per sample 8 bit mode 10 bit mode 1 to 1022 64 3FC, 3FC, 00
Video pixel range Black level value Escape sequence
1 to 254 16 FF, FF, 00
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480 pixels 484 pixels
VV6501 3.1.4 Digital data bus: D[4:0]
Functional Description
Sensor data may be either 8 or 10 bits per pixel and is transmitted as follows:
q q
10-bit data: A pair of 5-bit nibbles, most significant nibble first, on 5 wires. 8-bit data: A pair of 4-bit nibbles, most significant nibble first, on 4 wires. Figure 6: Digital data output modes
10-bit pixel data
5-wire output mode
D4,D3,D2,D1,D0
D9,D8,D7,D6,D5
D4,D3,D2,D1,D0
D9,D8,D7,D6,D5
8-bit pixel data 4-wire output mode
D3,D2,D1,D0 D7,D6,D5,D4 D3,D2,D1,D0 D7,D6,D5,D4
In 5-wire mode, the embedded control codes occupy only the most significant 8-bits, the least significant 2-bits are always zero.
Output tri-state using SIF
Register 23 bit[5] can be used to tri-state all 5 data lines, QCK and FST.
Output pad drive strength
The data and QCK output pads are tri-stateable with 4 mA drive.
3.1.5
Data qualification clock (QCK)
A data qualification clock (QCK) is available and complements the embedded control sequences. This clock runs continuously when enabled and consists of:
q
Fast QCK: the falling edge of the clock qualifies every 5 or 4-bit data blocks that constitute a pixel value. Slow QCK: the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that constitute a pixel value while the falling edge qualifies the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire mode, the rising edge of the clock qualifies the most significant nibbles while the falling edge of the clock qualifies the least significant nibbles. Figure 7: QCK modes
q
QCK (slow) QCK (fast) D[4:0]
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Functional Description 3.1.6 Line formats
VV6501
Each line of data from the sensor starts with an escape sequence followed by a line code that identifies the line type. The line code is then followed by two bytes that contain a coded line number. Each line is terminated with an end-of-line code followed by a line average. The one exception to this is the first line in the frame where the end of line code is followed by a frame count. Figure 8: Line data format
Start of Active Video (SAV) Escape/Sync sequence Line code Line number Video data End of Active Video (EAV) Escape/Sync sequence Line PixAv Null code Line padding SAV
Pixel number (unshuffled pixel data)
1
N pixels
N
4/5-wire data bus
FH 0H X H Y H D3 D2 D1 D0 P M P L PM PL FH 0H 8H 0H D3 D2 D1 D0 FH
The line code formats are detailed in Figure 9.
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VV6501
Figure 9: Line code format
5-wire output mode 4-wire output mode 1FH 1FH 1FH 1FH 00H 00H
Functional Description
FH
FH
FH
FH
0H
0H
XH
YH
D3
D2
D1
D0
Escape/sync sequence Supplementary data
At start of line: Line number (L11 MSB) Bit 7 0 6 5 4 3 L8 2 L7 1 L6 0 P Bit 7 0 6 L5
Line code see Table 3
5 L4
4 L3
3 L2
2 L1
1 L0
0 P Odd word parity
L11 L10 L9 Nibble D3
Nibble D2
Nibble D1
Nibble D0
At the end of the lines there are 2 possibilities: (i) First (Start of Frame) line: Frame Count (Fc7: MSB) Fc7 Fc6 Fc5 Fc4 Fc3 Fc2 Fc1 Fc0 Nibble D3 = FH Nibble D2 0 0 0 0 0 1 1 1
Nibble D1
Nibble D0
(ii) All other lines: Line Average (Av7 MSB) Av7 Av6 Av5 Av4 Av3 Av2 Av1 Av0 Nibble D3 = FH Nibble D2 0 0 0 0 0 1 1 1
Nibble D1
Nibble D0
The line code absolute value depends on whether 5-wire or 4-wire output mode has been selected, as shown in Table 3. Table 3: Line codes
Line code
Line codes at beginning of line
5-b Nibbles
4-b Nibbles
Start of Frame Blank Line (BL) Black or Dark line (BK) Visible Line (VL) Last line in Frame
Line Code at end of line
31CH (79610) 274H (62810) 2ACH (68410) 2D8H (72810) 368H (87210)
C7H (19910) 9DH (15710) ABH (17110) B6H (18210) DAH (21810)
End of Line
200H (51210)
80H (12810)
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Functional Description Start of frame line format
VV6501
The start of frame line contains the contents of the first 16 serial interface registers rather than any video data. This information immediately follows the line code at the beginning of the line. The code 07H is output after each serial interface value. It takes 32 pixel clock periods to output these 16 serial interface register values. The remaining pixel periods of the video portion of the line are padded out using 07H values. The first two pixel locations are also padded with 07H characters (Figure 10). If a serial interface register location is unused then the value from register 0 is output. Following the escape sequence and line code at the end of active video, a frame count is output. Figure 10: Start of frame line format
Start of Active Video (SAV)
Serial Interface Register Values
End of Active Video (EAV)
Start of frame line codes Data bus
FH 0H CH 7H 0H 1H 0H 1H
Padding characters
Frame count
0H 7H 1H 9H 0H 7H 4H 0H 0H 7H 0H 7H FH 0H 8H 0H D3 D2 D1 D0
FH
Line number 0
DeviceH (register 0)
DeviceL (register 1)
Active video line format All video data is contained on active video lines. The pixel data appears as a continuous stream of bytes within the active lines. Black line format The black lines contain information from the sensor black lines (held in zero exposure). This information may be used by certain co-processors. Dark line format The dark lines contain information from the sensor dark lines (shielded from light by metal). The information from these lines is used by the sensor to calculate a dark average offset value which is then applied to the video data to ensure a known `black' level for image data. Blank line format To reduce the frame rate it is possible to extend the frame length by adding blank data lines. These contain no video or black line data. In default VGA mode there are no blank lines. End of frame line format The end of frame line sole purpose is to indicate the end of a frame, it contains no video data.
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VV6501
Line Duration
Functional Description
Table 4 shows the image duration and interline intervals with default setup.
Table 4: Line timing
Image Sensor Clock 24MHz Pixel Clock QCKs 12MHz 644 s 53.6 QCKs 118 s 9.8 QCKs 762 s 63.5 Interline Line Total
Extending line lengths The user can extend the line length by writing to serial registers 82 and 83. The line length padding is inserted after the EAV sequence, ensuring that the distance between the SAV and EAV sequences remains constant.
3.1.7
Frame format
Each video frame is composed of a sequence of data lines as illustrated in Figure 11. Figure 11: VGA frame format
319 0 1 2 18 19 VGA frame = 524 lines
Start Of Frame Line
18 Black Lines
6 Dark Lines 24 25 26 484 Visible Lines 506 507 508 509 510 523 0 End Of Frame Line 14 Black Lines Start Of Frame Line
Extending the inter-frame period The user may choose to extend the inter-frame period by increasing the frame length by writing to serial registers 97 and 98. In this event, the appropriate number of additional blank lines is inserted between the End Of Frame (EOF) line and the Start Of Frame (SOF) line. This means that the distance between SOF and EOF remains constant.
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Functional Description
Timing of Frame Start signal (FST) The frame-level position of FST is illustrated in Figure 12. Figure 12: FST timing overview
VV6501
1 Frame Blanking Lines Blanking Lines Blanking Lines Start of Frame Start of Frame End of Frame
Visible Lines
Black Lines
FST:
The FST pulse qualifies the Status Line information and is 648 QCKs (slow) long. Figure 13: Detailed FST timing
Start of Frame Line Code Data Bus FST pin:
FH 0H CH 7H 0H 1H 0H 1H 0H 7H 1H 9H 0H 7H 4H 0H 0H 7H 0H 7H FH 0H 8H 0H D3 D2 D1 D0
Black Lines
FH
4 QCKs
644 QCKs
Frame start pulse qualifies status line: 648 QCKs
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VV6501 3.1.8 Image translations
Functional Description
The imaging array can be readout with different modes as described here below:
q q q
Shuffle horizontal readout, bit [7] of serial register [17]. Even columns (2,4,6.) are readout first. Mirror horizontal readout, bit [3] of serial register [22]. Columns are readout in reverse order. Mirror vertical readout, enabled by setting [4] of serial register [22]. Rows are readout in reverse order. Figure 14: Image readout modes
(a) Standard image readout
(b) Horizontal shuffle enabled
(c) Horizontal mirror enabled
(d) Vertical mirror enabled
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Functional Description 3.1.9 Dark calibration
VV6501
In order to produce a high quality output image from the VV6501, it is necessary to accurately control the black level of the video signal. There are two main sources of error:
q q
Dark current Offsets in the output path.
The black level is corrected by using dark pixel rows to "learn" the offset so that it can then be subtracted from the image data. Dark rows have the same exposure setting as the visible lines but are shielded from incident light. Figure 15: Overview of dark offset cancellation
Normal pixel Ilight + Idark Vpix Dpix Dark pixel Vpix Idark Dpix
Digital Logic Column 10-b ADC element + offset Offset cancellation
Column 10-b ADC element + offset
Learn offset + Idark
For 10-b data the ideal "black" code is set to be 64 (when viewing 8-b data the `black' code should be 16). The aim of the dark calibration algorithm is to "learn" the offset required such that "black" image lines have code 64. Figure 16: Role of dark offset calibration
Dark Line typ. value = 400
Dark calibration dark offset = 336
Dark Line
typ. value = 64
Image Line typ. value: 400 - 1360
Image Line typ. value: 64-1024
raw image
processed image
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VV6501 Dark calibration algorithm
Functional Description
The dark line monitoring logic accumulates a number of dark pixels, calculates an average and then compares this average with the appropriate black level. There is a bit in serial register 45 which determines whether the offset applied is the user-programmable value from serial register 44, or the value calculated by the offset cancellation processor. The dark offset cancellation algorithm accumulates data from the dark lines which is input to a leaky integrator and an appropriate offset is calculated. Following an exposure/gain change, on power up or when going out of suspend mode, the history in the dark calibration leaky integrator is reset to the incoming value as the previously stored value will be out of date.
User control
The serial interface allows the user the following additional controls:
q
Accumulate dark pixels, calculate dark pixel average and report, but do not apply anything to data stream Accumulate dark pixels, calculate dark pixel average, report and apply internally calculated offset to data stream Accumulate dark pixels, calculate dark pixel average and report, but apply a SIF supplied offset
q
q
3.1.10 Sensor clock and frame rate control
The frame rate is determined by both the input sensor clock and some additional registers under user control. Sensor clock The sensor requires a single-ended clock input. A 24MHz clock is required to generate 30 frames per second VGA images. The results is a pixel rate of 12MHz. Slower frame rates In order to achieve slower frame-rates the user has a number of options:
q q q
increase the inter-frame time by adding blank line (via SIF register) apply a slower external clock divide down the external clock using the sensor internal clock divider (via SIF register)
Clock divider The sensor contains a 4-bit register with which the user selects the clock divider setting (N). Table 5 gives the mapping between the clk_div value and the divider ratio. Table 5: User programmable clock divider values
clk_div[3:0] 0000 [default] 0001 001X 010X 011X 100X divide by 1 2 4 6 8 10 19/60
Functional Description
Table 5: User programmable clock divider values
clk_div[3:0] 101X 110X 111X divide by 12 14 16
VV6501
3.1.11 Exposure/gain control
The sensor does not contain any form of automatic exposure or gain control. To produce a correctly exposed image, exposure and gain values must be calculated externally and written to the sensor via the serial interface.
Exposure calculation
The exposure time for a pixel and the ADC range (therefore the gain) are programmable via the serial interface. The explanation below assumes that the gain and exposure values are updated together as part of a 5 byte serial interface auto-increment sequence. Exposure time combines coarse, fine exposure, pixel rate also related to frame and line lengths, all defined in Table 6. Table 6: Definitions related to exposure
Frame length
Number of lines per frame [default=524] The frame length may be increased to 1023 by writing to the frame length register. Number of pixels in a line [default = 762] The line length may be increased to 1023 by writing to the line length register. The pixel exposure time is determined by the course and fine exposure values The number of lines a pixel exposes for. Limited by frame length. Coarse exposure value is in the range [0 - (frame length -2)]. Number of additional pixel periods a pixel exposes for. Limited by line length. Fine exposure value is in the range [11 - (line length)]. Determined by the input clock frequency (Fclkin) and user clk_div setting. PixPeriod=(2*N)/Fclkin where N = clock divider ratio PixPeriod x [(Coarsenum_lines x Line_Lengthnum_pixels) + Finepixels]
Line length
Exposure Coarse exposure value
Fine exposure value
Pixel period
Exposure time
Example of exposure calculation in default VGA video mode coarse exposure = 522 fine exposure = 762 Input clock frequency - Fclkin = 24MHz, Pixel period = 2/(24 x 106) = 8.33 x10-8 s
Calculation: exposure time = 8.33 x10-8 x [(522 x 762) +762] = 33.2 ms
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VV6501
Functional Description
The available range of exposure (without using clock division) is shown in Table 7. Table 7: Exposure ranges [24MHz system clock]
Coarse (no. lines) 0 522 1023 Line length (no. pixels) 762 762 1023 Fine (no. pixels) 11 762 1023 Exposure No. pixels 0 400,050 10232 + 1023 Time 0.92 s 33.2 ms 87.3 ms
Range Min. Max (default-VGA) Max (available)
3.1.12 Gain timing and exposure updates
Exposure and gain values are re-timed within the sensor to ensure that a new set of values is only applied to the sensor array at the start of each frame. Bit 0 of the status register is set high when a new exposure value is written via the serial interface but has not yet been applied to the sensor array. There is a 1 frame latency between a new exposure value being applied to the sensor array and the results of the new exposure value being read-out. The same latency does not exist for the gain value. To ensure that the new exposure and gain values are aligned up correctly the sensor delays the application of the new gain value by one frame relative to the application of the new exposure value. To eliminate the possibility of the sensor array seeing only part of the new exposure and gain settings, if the serial interface communication extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the exposure page of the serial interface register map. Thus, if the 5 bytes of exposure and gain data is sent as an autoincrement sequence, it is not possible for the sensor to consume only part of the new exposure and gain data.
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Functional Description
VV6501
3.2
Audio block
The audio amplifier is designed to drive an external ADC, possibly in the co-processor, with an amplified audio signal taken from a FET microphone input. The 3-bit gain control and power down for the reference are controlled via the I2C interface. Figure 17: VV6501 audio amplifier overview
Power management AUD3V3 Digital block AUDGAIN[2:0] pdaudref Audio Bandgap
+ -
Audio amplifier
+
-
AUDOUTP
x1
x1
+
AUDOUTN
AUDREF
MICBIAS
MICIN
micro
3.2.1
Co-processor support for audio
Table 8 below summarizes the audio capability of the different co-processors the VV6501 is intended to work with.
Table 8: Co-processor support for audio
Co-processor STV0676 STV0674
Audio support Audio 8-b digital endpoint 16 bit Sigma-Delta External ADC needed
Comment
501 audio output is directly AC coupled to STV0674 differential audio inputs. STV0674 includes digital ALC and noise gate
STV0680/1
Successive approximation ADC
Low quality audio recording support
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VV6501 3.2.2 Audio amplifier key features
q
Functional Description
Very high PSRR micro bias reference due to bandgap from the 3.3V regulated supply, as well as RC network for LF filtering in the audio bandwidth. Fully differential low-noise amplifier with gain control via serial IF (0dB to +42dB in 6dB steps).
q
Up to 1.8Vpp dynamic range on AUDOUTP and AUDOUTN Figure 18: VV6501 audio amplifier in typical application
V5V
Audio regulator
Power management
AUD3V3 2.2uF
AUD3V3 Audio AUDREF 100nF 1 MICBIAS buffer x1.3 Audio bandgap pd AUDOUTP Cc 220nF AUDOUTN Cc 220nF differential ADC
50K 50K
STV0674
Gain[2:0] 0:42dB
input stage
R
MICIN Electret Mic Cin 470nF
LNA
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Functional Description
VV6501
3.3
3.3.1
Power management
Voltage regulators
The power management block on the device avoids the requirement for any external system regulators in a 5 V based camera product. The scheme is shown in Figure 19.
q
Digital Regulator 1 - This 5 V to 3.3 V regulator uses an external bipolar transistor to supply loads up to 200 mA. It is typically used to power the sensor digital logic and may also be used to supply an external co-processor if required. This regulator is always on. Digital Regulator2 - This 3.3 V to 1.8 V regulator uses an external bipolar transistor to supply loads up to 100 mA. This supply may be used for an external co-processor if required. This regulator is controlled by the PDREG1V8 pin and must be switched off if not required. Audio Amp Regulator - This 5 V to 3.3 V regulator supplies the audio amplifier and the buffer amplifier used to supply the reference to the microphone (Load 5 mA). It should be externally decoupled with a 2.2 F capacitor. For applications without audio this regulator may be powered down via the SIF registers. Video Regulator - This 5 V to 3.3 V regulator supplies the analogue video circuitry. It should be externally decoupled with a 2.2 F capacitor. Figure 19: Voltage regulator block diagram
q
q
q
VV6501
Power management block V5V
5V 5V Bandgap vbg VBG 5V Dig Reg1 + vbg VBASE3V3 VDIG3V3 VDD VDD 3V Dig Reg2 + vbg pd 5V VidReg + vbg pd VID3V3 6.8nF
1F
4-5.5V
Digital block
ZTX749 3v3 10F
IO (3V3)
coprocessor
1v8 ZTX749
core (1v8)
VBASE1V8 VDIG1V8
PDREG1V8
pdreg2
10F
pdvidreg pdaudreg Video block Voltage doubler Audio amplifier
5V AudReg + vbg pd AUD3V3
2.2F
2.2F
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VV6501 3.3.2 Power-on reset cell
Functional Description
The power-on reset cell generates a low going pulse whenever the digital power supplies are below their lower limits. The power-on reset signal resets the sensor internally and is also available on the PORB pin and may be used to reset a co-processor. The PORB cell monitors both the 3V3 and 1V8 supplies. If the 1V8 supply is not required then PDVREG1V8 must be tied high. Figure 20: Power-on reset block
Regulated supply Threshold PORB
3 V/1V8 0V
PORB block 3V3 power-on reset cell 1V8 power-on reset cell
VDIG1V8 PDREG1V8
000000
000000
00000
CLKIN VDIG3V3
PORB
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Functional Description
VV6501
3.4
3.4.1
Device operating modes
Power-up
On power up the sensor is in low-power mode. All data bus lines drive high to indicate that the device is "present".
3.4.2
Waking up the sensor
The sensor is made to exit low power mode by enabling the external clock and writing to SIF register16 bit 0. The first frame output after exiting low-power mode does not contain any valid video data. Figure 21: Exiting low-power mode
LP1 LP2 LP3
LP4 0
Valid video data.
D[4:0]
FH
9H,6H,9H,6H...
One frame of 9H & 6H data. CLKIN SDA SCL setup0[0] Frame number
Start of frame line for the 1st frame of valid video data.
1
2
LP1 LP2-LP3
D[4:0] are set to FH and the sensor analogue circuitry is powered down. "Exit low power mode" command. Powers-up analogue circuits and initiates the 1 frame start-up sequence 1 frame of alternating 9H & 6H data on D[4:0] The sensor is being initialized during this frame.
LP3-LP4
3.4.3
Low power mode
Entering low-power mode during video streaming causes the analogue circuits to be powered down. The values of the serial interface registers is preserved.
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VV6501 3.4.4 Suspend mode
Functional Description
Suspend mode is the lowest possible power consumption mode with current < 100 A. In suspend mode the external clock is gated inside the device and the analogue blocks are powered down. The sensor is set into suspend mode by driving the SUSPEND pin high. To achieve the lowest possible power consumption, the clock source should also be turned OFF for the duration of the SUSPEND mode.
3.4.5
Sensor soft reset
All the serial interface registers may be reset to their default values by setting the "soft reset" bit (bit 2) of setup register 0. This causes the sensor to enter low power mode.
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Serial Control Bus
VV6501
4
4.1
Serial Control Bus
General description
The 2-wire I2C serial interface bus is used to read and write the sensor control registers. Some status registers are read-only. The main features of the serial interface include:
q q q q q
Variable length read/write messages. Indexed addressing of information source or destination within the sensor. Automatic update of the index after a read or write message. Message abort with negative acknowledge from the master. Byte oriented messages.
4.2
Serial communication protocol
The co-processor must perform the role of communication `master' and the sensor acts as a `slave'. The communication from host to sensor takes the form of 8-bit data with a maximum serial clock frequency of 100 kHz. Since the serial clock is generated by the bus master it determines the data transfer rate. Data transfer protocol on the bus is illustrated in Figure 22. Figure 22: Serial Interface data transfer protocol
Acknowledge
Start condition
SDA
MSB
SCL S
LSB 2 3 4 5 6 7 8
P
1
A Stop condition
Address or data byte
4.2.1
Data format
Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal data is produced by sampling sda at a rising edge of scl. The external data must be stable during the high period of scl. Exceptions to this are start (S) or stop (P) conditions when sda falls or rises respectively, while scl is high. A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (Sr) followed by another message.
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VV6501
Serial Control Bus
The first byte contains the device address byte which includes the data direction read, (r), ~write, (~w), bit. Figure 23: VV6501 Serial interface address
0
0
1
0
0
0
0
R/W
The byte following the address byte contains the address of the first data byte (also referred to as the index). The serial interface can address up to 128 byte registers. If the MSB of the second byte is set, the automatic increment feature of the address index is selected. Figure 24: Serial interface data format
Sensor acknowledges valid address S address[7:1] address [0] A A
Acknowledge from slave
DATA[7:0]
INC
INDEX[6:0]
A
R/
W bit
Auto increment Index bit
DATA[7:0]
A
P
4.2.2
Message interpretation
All serial interface communications with the sensor must begin with a start condition. If the start condition is followed by a valid address byte then further communications can take place. The sensor will acknowledge the receipt of a valid address by driving the sda wire low. The state of the read/~write bit (LSB of the address byte) is stored and the next byte of data, sampled from sda, can be interpreted. During a write sequence the second byte received is an address index and is used to point to one of the internal registers. The MSB of the following byte is the index auto increment flag. If this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. The master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start, (Sr). If the auto increment feature is used the master does not have to send indexes to accompany the data bytes. As data is received by the slave, it is written bit by bit to a serial/parallel register. After each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. During a read message, the current index is read out in the byte following the device address byte. The next byte read from the slave device are the contents of the register addressed by the current index. The contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. Although VV6501 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor.
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Serial Control Bus
VV6501
At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater than the last location read from or written to. A subsequent read will use this index to begin retrieving data from the internal registers. A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation.
4.3
Types of messages
This section gives guidelines on the basic operations to read data from and write data to the serial interface. The serial interface supports variable length messages. A message may contain no data bytes, one data byte or many data bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions available are detailed below.
q q
Write no data byte, only sets the index for a subsequent read message. Multiple location write (using auto increment index bit) for fast information transfers.
Examples of these operations are given below. A full description of the internal registers is given in the previous section. For all examples, the slave address used is 3210 for writing and 3310 for reading. The write address includes the read/write bit (the LSB) set to zero while this bit is set in the read address.
4.3.1
Single location, single data write
When a random value is written to the sensor, the message looks as shown in Figure 25. Figure 25: Single location, single write
Start S
Device address 20h
Ack A0
Index 32h A
Data 85h A
Stop P
In this example, the fineH exposure register (index = 3210) is set to 8510. The r/w bit is set to zero for writing and the Inc. bit (MSB of the index byte) is set to zero to disable automatic increment of the index after writing the value. The address index is preserved and may be used by a subsequent read. The write message is terminated with a stop condition from the master.
4.3.2
Single location, single data read
A read message always contains the index used to get the first byte. Figure 26: Single location, single read
Start S
Device address 21h
Ack A0
Index 32h A
Data 85h A
Stop P
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VV6501
Serial Control Bus
This example assumes that a write message has already taken place and the residual index value is 3210. A value of 8510 is read from the fineH exposure register. Note that the read message is terminated with a negative acknowledge (A) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition.
4.3.3
No data write followed by same location read
When a location is to be read and the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to another master, a repeated start condition is asserted between the write and read messages. In this example, the gain value (index = 3610) is read as 1510 (see Figure 27). Figure 27: No data write followed by same location read
No data write S 21h A0 36h A Sr 21h
Read index and data A0 36h A 15h AP
As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master.
4.3.4
Multiple location write
If the automatic increment bit is set (MSB of the index byte), it is possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. An auto-increment write to the exposure registers with their default values is shown in Figure 28. Figure 28: Multiple location write
Incremental write S 20h A1 10h A 11h A C1h AP
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I2C Registers
VV6501
5
5.1
I2C Registers
Register map
Sensor registers may be split into 5 main categories:
q q q q q
Status Registers (read only) Setup registers with bit significant functions Exposure parameters that influence output image brightness Video timing functions Audio functions
Any internal register that can be written to can also be read from. There are a number of read only registers that contain device status information, (for example design revision details). Names that end with H or L denote the most or least significant part of the internal register. Note that unused locations in the H byte are packed with zeroes. A detailed description of each register follows. The address indexes are shown as decimal numbers in brackets [ ]. Note that there are many unused register locations.
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VV6501
Table 9: Serial interface address map
Index Name Length R/W Default Comments
I2C Registers
Status registers
0x00 0x01 0x02 0x09 0x0A deviceH deviceL status0 dark_avgH dark_avgL 8 8 8 4 8 RO RO RO RO RO 0x1F 0x50 0x10 0 0 Chip identification number including revision indicator (501 Rev0). Status information This is the average pixel value returned from the dark line offset cancellation algorithm (2's complement notation) Current frame count (0-255)
0x0E
frame counter
8
RO
Setup registers
0x10 0x11 0x14 0x15 0x16 0x17 setup0 setup1 fg_modes pin_mapping vshuffle/mirrors op_format 8 8 8 7 8 7 R/W R/W R/W R/W R/W R/W 0x1 0x80 0 0 0 0x18 Low-power and video timing Various parameters FST and QCK setup FST and QCK mapping modes Read-out order of data Output coding formats
Exposure registers
0x20 0x21 0x22 0x23 0x24 0x25 0x2C 0x2D 0x2E fineH fineL coarseH coarseL analogue gain clk_div dark offsetH dark offsetL dark offset setup 2 8 2 8 4 4 3 8 3 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x61 0 0 Analogue gain setting Clock division Dark line offset cancellation value (2's complement notation) Dark line offset cancellation enable 0x20A Coarse exposure 0 Fine exposure
Video timing registers
0x52 0x53 0x54 0x55 line_lengthH line_lengthL frame_lengthH frame_lengthL 2 8 2 8 R/W R/W R/W R/W 0x20B Frame length (lines) 0x2F9 Line length (pixel clocks)
Audio register
0x79 audio 4 R/W 0x9 Audio setup register
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I2C Registers
VV6501
5.2
5.2.1
Register description
Status registers
[0x00-0x01] - DeviceH and DeviceL These registers provide read only information to identify the sensor type that has been coded as a 12-bit number and a 4-bit mask set revision identifier. The device identification number for VV6501 is 501 equivalent to 0001 1111 01012. The initial mask revision identifier is 0 equivalent to 0000 2. Table 10: [0x00] - DeviceH
Bits [7:0] Function Device type identifier Default 0x1F Comment Most significant 8 bits of the 12 bit code identifying the chip type.
Table 11: [0x01] - DeviceL
Bits [7:4] [3:0] Function Device type identifier Mask set revision identifier Default 0x5 0 Comment Least significant 4 bits of the 12 bit code identifying the chip type.
[0x02] - Status0
Bit 7 [6:5] 4 3 2 1 0 Function Video timing parameter update pending flag RESERVED Odd/even frame Clock division update pending Gain value update pending Coarse exposure value update pending Fine exposure value update pending 0x1 0 0 0 0 The flag will toggle state on alternate frames Clock divisor sent but not yet consumed by the sensor Gain value sent but not yet consumed by the sensor Coarse exposure value sent but not yet consumed by the sensor Fine exposure value sent but not yet consumed by the sensor Default 0 Comment Video timing parameters sent but not yet consumed by sensor
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VV6501
[0x09-0x0A] - Dark_Avg
Register Index 10 9 Bits [7:0] [1:0] Function Dark avg ls byte Dark avg ms bits Default 0 0 Comment
I2C Registers
The calculated pixel average over a series of dark lines.
[0x0E] - Frame Counter
Register index 14 Bits [7:0] Function Frame count Default 0 Comment Increments by 1 at each frame
5.2.2
Setup Registers
[0x10] - Setup0
Bit [7:5] [4:3] 2 1 0 Function Video Timing Mode RESERVED Soft Reset Off / On RESERVED Low Power Mode: Off / On 0x1 Powers down the sensor array and audio. The output data bus goes to FH. On power-up the sensor enters low power mode. 0 Setting this bit resets the sensor to its power-up defaults. This bit is also reset. Default 0x1 VGA Mode Comment
[0x11] - Setup1
Bit 7 Function Pixel read-out order (hshuffle) Unshuffled or Shuffled [6:5] 4 RESERVED Enable immediate gain update. Off/On 3 [2:0] Enable immediate clock division update. Off/On RESERVED 0 Allow manual change to clock division to be applied immediately 0 Allow manual change to gain to be applied immediately Default 1 Comment Shuffle is enabled by default
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I2C Registers
[0x14] - fg_modes
Bit [7:6] [5:4] [3:2] Function FST mode RESERVED QCK modes 0 00 - Off 01 - Free running 1x - Valid during data period only 1 0 RESERVED QCLK type 0 0 - slow_QCLK/ 1 - fast_QCLK Default 0 Comment 0 - Off 1 - On - qualifies the status line
VV6501
[0x15] - pin_mapping
Bit 7 6 5 [4:3] 2 1 0 Function RESERVED reset_flag. RESERVED RESERVED Forced value for FST pin Forced value for QCLK pin Map serial interface register bits values on to the QCK and FST pins. 0 0 0 only when enabled by bit0 only when enabled by bit0 Select data to appear on FST and QCK pins 0 - FST and QCK signals (default) 1 - pin_mapping[2] and pin_mapping[1] 1 Set to 1 by porb, reset_n soft_reset. The user can clear this bit by writing to SIF. Default Comment
[0x16] - Vshuffle/mirrors
Bit [7:5] 4 3 [2:0] Function RESERVED Line read-out order (vmirror) Normal or Mirrored Pixel read-out order (hmirror) Normal or Mirrored RESERVED 0 0 Default Comment
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VV6501
[0x17] - op_format
Bit 7 6 Function RESERVED Re-time tri-state update. Off / On 5 Tri-state output data bus, FST & QCLK Outputs Enabled / Tri-state [4:3] 2 RESERVED Embedded SAV/EAV Escape Sequences On / Off 0 0 0 Default Comment
I2C Registers
Re-time new tri-state value to a frame boundary.
On power up the data bus, QCLK & FST pads are enabled by default.
0 - Insert Embedded Control Sequences e.g Start and End of Active Video into Output Video data 1 - Pass-through mode. Output Video data equals ADC data. Note: also disables FST when SAV/EAV generation disabled.
1 0
RESERVED Data format select. 0 0 - 5 wire parallel output 1 - 4 wire parallel output
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I2C Registers 5.2.3 Exposure control registers
VV6501
There is a set of programmable registers which control the sensor sensitivity. The registers are as follows:
q q q q
Fine exposure Coarse exposure time Analogue gain Clock division
The gain parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core.
Note:
The external exposure (coarse, fine, clock division or gain) values do not take effect immediately. Data from the serial interface is read by the exposure algorithm at the start of a video frame. If the user reads an exposure value via the serial interface, then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor.
Between the writing the of exposure data and the use of the data by the exposure logic, bit 0 of the status register is set. The gain value is updated a frame later than the coarse, fine and clock division parameters, since the gain is applied directly at the video output stage and does not require the long set up time of the coarse, fine exposure and of the clock division. To eliminate the possibility of the sensor array seeing only part of the new exposure and gain settings, if the serial interface communication extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the exposure page of the serial interface register map. Thus if the 5 bytes of exposure and gain data is sent as an autoincrement sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. The range of some parameter values is limited and any value programmed out of the range is clipped to the maximum allowed. Table 12: Exposure, clock rate and gain registers
Register index 0x20 0x21 0x22 0x23 0x24 0x25 0x2C 0x2D 0x2E Bits 0 [7:0] 0 [7:0] [7:0] [3:0] [1:0] [7:0] [7:0] Function Fine MSB exposure value Fine LSB exposure value Coarse MSB exposure value Coarse LSB exposure value Analogue gain value Clock divisor value Dark offsetH Dark offsetL Dark offset control register 0 0 0 0 0 0x20A Frame length dependent. Maximum for default modes: VGA = 522 Bits[3:0] IDAC control See [0x25] - Clock divider setting for details Dark offset manual settings Default 0 Comment Line length dependent
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VV6501
[0x20] - Fine exposure MSB
Bit [7:2] [1:0] Function RESERVED Fine Exposure [9:8] 0 Default Comment
I2C Registers
[0x21] - Fine exposure LSB
Bit [7:0] Function Fine Exposure [7:0] 0 Default Comment
[0x22] - Coarse exposure MSB
Bit [7:2] [1:0] Function RESERVED Coarse Exposure [9:8] 0x2 Default Comment
[0x23] - Coarse exposure LSB
Bit [7:0] Function Coarse Exposure [7:0] Default 0xA Default = 522 Comment
[0x24] - Analogue gain/ offset
Bit [7:4] [3:0] Function RESERVED GAIN [3:0] 0 0000 = 1.0, Min. Gain = (0dB) 0001 = 1.06 0010 = 1.14 0011 = 1.23 0100 = 1.33 0101 = 1.45 0110 = 1.60 0111 = 1.78 1000 = 2.0 1001 = 2.29 1010 = 2.67 1011 = 3.2 1100 = 4.0 1101 = 5.33 1110 = 8.0 1111 = 16, Max Gain = (24dB) Default Comment
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I2C Registers
[0x25] - Clock divider setting
Bit [7:4] [3:0] Function RESERVED Clock divider setting 0 0000 - Divide clock by 1 0001 - Divide clock by 2 001x - Divide clock by 4 010x - Divide clock by 6 011x - Divide clock by 8 100x - Divide clock by 10 101x - Divide clock by 12 110x - Divide clock by 14 111x - Divide clock by 16 Default Comment
VV6501
[0x2C -0x2D] - Dark line pixel offset
Bit [7:0] [2:0] Function LS Dark line pixel offset MS Dark line pixel offset Default 0 Comment This register contains a fixed offset that can be applied to the digitised pixels in the digital output coding block. The offset is a 2's complement number, giving an offset range -1024,+1023.
[0x2E] - Dark line offset cancellation setup register
Bit 7 [6:4] 3 2 [1:0] Function RESERVED RESERVED Dark leaky integrator time constant RESERVED Dark line offset cancellation 01 00 - Accumulate dark pixels, calculate dark pixel average and report, but don't apply anything to data stream 01 - Accumulate dark pixels, calculate dark pixel average, report and apply internally calculated offset to data stream 11 - Accumulate dark pixels, calculate dark pixel average and report, but apply an externally calculated offset 0 0 - Fast 1 - Slow Default Comment
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VV6501 5.2.4 Video timing registers
I2C Registers
Indexes in the range [0x52 - 0x62] control the line and frame length of the sensor. The registers are as follows:
q q
line length frame length
The line length is specified in a number of pixel clocks, whereas the frame length is specified in a number of lines.The range of some parameter values is limited and any value programmed out of the range is clipped as follows:
q q
Values greater than the maximum are clipped to the maximum allowed. Values less than the default for a given mode are clipped to the default value. Table 13: Video timing registers
Register index 0x53 0x52
Bit [7:0] [7:2] [1:0]
Function Line Length LSB value RESERVED Line Length MSB value Frame Length LSB value RESERVED Frame Length MSB value
Default 0xF9
Comment
0x2 0x0B
Default = 761 Maximum = 1023 (register value is line length - 1)
0x62 0x61
[7:0] [7:2] [1:0]
0x2
Default = 523 Maximum = 1023 (register value is frame length - 1)
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I2C Registers 5.2.5 Audio setup register
[0x79] - Audio amplifier setup (AT1)
Bit 7 6 [5:4] 3 [2:0] Function Retro gain mode select Power down audio ref. only RESERVED Power down amp. and ref. Audio amplifier gain 0 1 0 - Powered up 1 - Power down Default 0 0 Comments 0 - Retro gain mode 1 - Standard gain mode
VV6501
Table 14: Audio gain options
Retro gain mode ([[7]=0) reg121[2:0] Gain 000 001 010 011 100 101 110 111 0dB 30dB 6dB 36dB 12dB 42dB 18dB 24dB AUDGAIN[2:0] 000 101 001 110 010 111 011 100 Gain 0dB 6dB 12dB 18dB 24dB 30dB 36dB 42dB AUDGAIN[2:0] 000 001 010 011 100 101 110 111 Standard gain mode ([7]=1)
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VV6501
Electrical Characteristics
6
6.1
Electrical Characteristics
Absolute maximum ratings
Table 15: Absolute maximum ratings Symbol VDD VDD VCC TSTO TLEAD Parameter Regulator input power voltage Digital power supply Analogue power supply Storage temperaturea Lead temperature (10 s) JDEC moisture level 3 Max. -0.5 to 6.0 -0.5 to 3.6 -0.5 to 3.6 -25 to + 85 225 Unit V V V
oC
C
a. A temperature below 0C can induce a slight humidity penetration into the package cavity. This humidity is easily removable by a short storage in standard climatic conditions (25C/50% relative humidity).
Caution: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.2
Operating conditions
Table 16: Operating conditions Symbol VDD TA Supply voltage Ambient temperature Parameter Max. 4.1 to 5.5 0 to +40 Unit V C
6.3
Thermal data
Table 17: Thermal data
Symbol Rth(j-a) Parameter Junction/ambient thermal resistance Value 45 Unit C/W
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Electrical Characteristics
VV6501
6.4
DC electrical characteristics
Over operating conditions unless otherwise specified.
6.4.1
Power supply
Table 18: Power supply characteristics
Symbol VBUS IVBUS ISUSP Parameter description Power supply range of operation Normal mode sensor current consumption (VGA 30 fps - no load on digital regulators) Current consumption in SUSPEND mode (SUSPEND pin high) and VDIG1V8 disabled. 65 140 A Min. 4 Typ. 5 25 Max. 5.5 50 Unit V mA
6.4.2
Digital block
Table 19: Digital block electrical characteristics
Symbol
CMOS digital inputs
Parameter description
Min.
Typ.
Max.
Unit
VIL VIH IIL IIH
Low level input voltage High level input voltage Low level input current High level input current 2
0.8
V V
-1 1
A A
CMOS digital outputs
VOL VOH
Low level output voltage High level output voltage 2.8
0.2
V V
Serial interface
FSIF
Operating frequency range
0
100
kHz
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VV6501 6.4.3 Regulators
Electrical Characteristics
Table 20: Electrical characteristics of regulators
Symbol
5V bandgap
Parameter description
Min.
Typ.
Max.
Unit
VBG IBG
Bandgap voltage Bandgap current drive capability
1.08
1.2 10
1.38
V A
Digital regulator 1
VDIG3V3 ILOAD PSRR
Regulated output voltage, (ILOAD < 300 mA) Output current drive capability 10 Hz < Freq <10 kHz, C = 1 F, relative to Vbus voltage swing over operating range
3.0
3.3 200
3.6 300
V mA dB
40
Digital regulator 2
VDIG1V8 ILOAD PSRR
Regulated output voltage (ILOAD < 50 mA) Output current drive capability 10 Hz < frequency <10 kHz, C = 1 F, relative to Vbus voltage swing over operating range
1.62 40
1.8 100
1.98 200
V mA dB
Audio and video regulators
VVIDEO IVIDEO VAUDIO IAUDIO
3.3 V video regulator Video current drive capability 3.3 V audio regulator Audio current drive capability
3.0
3.3 10
3.4
V mA
3.0
3.3 5
3.4
V mA
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Electrical Characteristics 6.4.4 Audio amplifier
Table 21: Audio amplifier electrical characteristics
Symbol
Audio reference
VV6501
Parameter description
Min.
Typ.
Max.
Unit
RAUDREF IAUDREF
Output impedance of audio reference ILOAD < 100 A Audio reference drive capability
100 1
k A
Microphone bias
VMICBIAS IMICBIAS RMICBIAS
Microphone bias voltage Microphone bias drive capability Micro biasing voltage output impedance (IMICBIAS < 500 A)
1.4
1.6 500 100
1.8
V A W
Microphone input
RMICIN VMICIN
Amplifier
Microphone input impedance Microphone input DC voltage
40 1.6
k V
GAIN
Overall gain (OUTP or OUTN) / MICIN According to I2C settings Output dynamic voltage swing (OUTP / OUTN) Harmonic distortion on OUTP & OUTN 1 kHz, 1.8 VPP output. Output DC common voltage Output impedance (OUTP / OUTN) ILOAD < 300 A Input equivalent noise BW 20 Hz to 20 kHz / source impedance = 2.2k Voltage supply rejection (diff: OUTP - OUTN) 42dB gain, +/-200mV ripple on AUD3v3 @ 1 kHz Voltage supply rejection (OUTP / OUTN) 42dB gain, +/-200mV ripple on AUD3v3 @ 1 kHz Low cut-off frequency (CIN = 2.2 F) High cut-off frequency
0
42
dB
DynOut THD DCout ROUT En
1.8 0.1 1.6 100 1.5
Vpp % V uVrms
PSR (diff) PSR (single) LFc HFc
40 40 20 20
dB dB Hz kHz
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VV6501
Electrical Characteristics
6.5
AC electrical characteristics
Table 22: Serial interface timing
Symbol fSCL Parameter SCL clock frequency Max. 100 Unit kHz
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Optical Characteristics
VV6501
7
7.1
Optical Characteristics
Optical characterisation methods
The following measurements are made based on the pixel as summarized in Table 23. Table 23: VV6501 Pixel overview
Parameter Size Architecture Saturation voltage at pixel, VSAT (Gain x1, 1024 codes) FD capacitance 3.0 fF Value 5.6 x 5.6 3T, DDS 1.2 V Unit m
Average sensitivity
The average sensitivity is a measure of the image sensor response to a given light stimulus. The optical stimulus is a white light source with a color temperature of 3200K, producing uniform illumination at the surface of the sensor package. For a color sensor, an IR blocking filter, CM500, is added to the light source. The analog gain of the sensor is set to x1. The exposure time, t, is set as 50% of maximum. The illuminance, I, is adjusted so the average sensor output code, Xlight, is roughly mid-range equivalent to a saturation level of 50%. Once Xlight has been recorded the experiment is repeated with no illumination to give a value Xdark.
Xlight - Xdark The sensitivity is then calculated as -------------------------------------- . The result is expressed in volts per lux-second. t I
Dark signal
The dark signal is a measure of the effect of pixel leakage current on the sensor output. The measurement is performed without illumination. As the dark signal is small the analog gain, G, of the sensor is increased to x4. For the same reason the clock divisor is set to16. As the leakage is highly temperature dependent, measurement is done at a controlled temperature of 25oC. The mean sensor output is then recorded at 2 exposure settings: Xdark at the maximum exposure time; Xblack at zero exposure.
The dark signal is calculated as ---------------------------------------- and is expressed in volts per second. Xdark - Xblack t G
Temporal noise of pixel and readout
A measure of the temporal noise is required to quantify the noise floor. As the signal is small the gain, G, is set to the maximum of x16. In order to remove fixed pattern noise sources it is calculated as the standard deviation, black, of the difference of a pair of zero exposure and zero illumination images. Random noise is expressed in mV.
Dynamic range
The dynamic range is the measure of the maximum and minimum signal levels at which the sensor can be used. The figure for temporal noise is used to find the dynamic range as follows 20 log y -------------------- .
G Vsat black
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VV6501 Sensor SNR
Optical Characteristics
The SNR measurement given here is based on the temporal noise. The SNR is calculated as the pixel saturation voltage divided by the temporal noise at that saturation level. The optical setup is the same as for the measurement of average sensitivity. The sensor gain, G, is set to x1. The SNR figure is then calculated as: 20 log G Vsat . -------------------y
signal
Fixed Pattern Noise (FPN)
The FPN of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. The illumination source is the same as for the average sensitivity measurement. The FPN is calculated at coarse exposure settings of 0,10,150,250 and 302 with a gain set to 1. 10 frames are grabbed and averaged to produce a temporally independent frame before each calculation. FPN is expressed in mV.
Vertical Fixed Pattern Noise (VFPN)
VFPN describes the spatial noise in an image sensor related to patterns with a vertical orientation. The VFPN is defined as the standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero illumination. VFPN is expressed in mV.
Shading
Shading describes how average pixel values per "block" change across the image sensor array. For fine shading calculations, the image sensor array is split into 30 pixel by 30 pixel blocks. An average value is then calculated for each block, averages are then compared across the whole device. The blocks are increased in size to 60 pixels by 60 pixels for the gross shading calculation. Shading is expressed in mV.
7.2
Optical characterisation results
Table 24: Optical characterization
Optical parameter Average sensitivity Dark signal Temporal noise Dynamic Range SNR Fixed Pattern Noise Vertical fixed pattern noise Shading (Gross) Red 1.1 Green 2.05 9.0 2.12 54 41 1.13 0.68 1.3 Blue 1.0 Unit V/lux.s mV/s mV dB dB mV mV %
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Optical Characteristics
VV6501
7.3
Spectral response
The spectral response measurement is given below. Figure 29: Spectral response
2000 Response (V/s) / (W/m2) 1500 1000 500 0 -500 Wavelength in nm red green1 green2 blue
400
500
600
700
800
900
1000
7.4
Blooming
We do not perform any test measurements for blooming. Blooming is a phenomenon that does not affect CMOS sensors the same way as CCD imagers are afflicted. CCD blooming can cause an entire column or set of columns to flood and saturate.
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VV6501
Defect Categorisation
8
8.1
Defect Categorisation
Introduction
Two distinct categories of defects are discussed in this section:
q q
Pixel defects (Section 8.2 - Section 8.5) Physical aberrations (Section 8.6)
The two categories differ in terms of test methodology as explained below.
8.2
Pixel defects
All packaged CMOS image sensors can contain impurities, either silicon faults, optical blemishes or external dirt particles which can be introduced in the product at various stages of the manufacturing process. These impurities can result in pixel defects, that is a pixel whose output is not consistent with the level of incident light falling on the image sensor. Precise definitions of the type of pixel defect tested by STMicroelectronics are outlined below. The ability to identify and correct these defects is central to both the design requirements and quality certification, via test of STMicroelectronics sensor products. STMicroelectronics produces a number of hardware co-processors and software drivers that implement defect correction algorithms. The defect correction algorithms ensure that the VV6501 sensor in conjunction with a companion STMicroelectronics co-processor will produce a high quality final image.
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Defect Categorisation
VV6501
8.3
Sensor array area definition
For specific aspects (refer to couplet test, see Section 8.4.3) of pixel defect testing, the image sensor array is subdivided into two regions as follows: Figure 30: VV6501 array
Inner area
242 pixels
484 pixels
Outer area
322 pixels 644 pixels
The inner array in Figure 30 above is centre justified, in the x and y axis, with respect to the outer array. The inner array is 50% of the full width and 50% of the full height of the larger outer array, therefore the inner array is one quarter of the area of the outer array.
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VV6501
Defect Categorisation
8.4
8.4.1
Pixel fault definitions
Pixel fault numbering convention
Please find the pixel notation described in Figure 31 below. For test purpose, the 3x3 array describes 9 Bayer pixels of a common color, that is all the pixels will either be Red, Green or Blue. The pixel under test is X. Figure 31: Pixel numbering notation
[0] [7] [6]
[1] X [5]
[2] [3] [4]
8.4.2
Single pixel faults
STMicroelectronics define a single pixel fail as a failing pixel with no adjacent failing neighbors of the same colour. A single pixel fail can be a "stuck at white" where the output of the pixel is permanently saturated regardless of the level of incident light and exposure level, a "stuck at black" where the pixel output is zero regardless of the level of incident light and exposure level or simply a pixel that differs from its immediate neighbors by more than the test threshold, that is differ by more than 8.0% from pixel average of color space neighbors. In the example below in Figure 32, we assume that the pixel `X' is a fail. This pixel is qualified as single pixel fail if the pixels at positions [0],[1],[2],[3],[4],[5],[6] and [7] are "good" pixels that pass the final test. The implemented test program qualifies a sensor with up to 120 single pixel faults. Defect correction algorithms correct the single pixel faults in the final image. Figure 32: Single pixel fault
[0] [7] [6] [1] X [5] [2] [3] [4]
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Defect Categorisation 8.4.3 Couplet definition
VV6501
A failing pixel at X with a failing pixel at position [0] or [1] or [2] or [3] or [4] or [5] or [6] or [7] such that there is a maximum of 2 failing pixels from the group of 9 pixels illustrated in Figure 33 is described as a couplet fail. The example shown on the right in Figure 33 has failing pixels at the centre location and at position [7]. Figure 33: General couplet examples
[0] [7] [6] [1] X [5] [2] [3] [4] [0] X [6] [1] X [5] [2] [3] [4]
The basic couplet definition is further subdivided into minor and major couplets. With respect to the example in Figure 33, a minor couplet is defined as a defect pixel pair where one pixel can be an extreme fail, that is a "stuck at black" or "stuck at white", but the second pixel in the pair must differ from the local pixel average by less than 15% of that average value. If the second pixel in the couplet differs by more than 15% of the local pixel average value then this would be defined as a major couplet. Note that the test program considers a couplet as 2 independent pixels. If the test identifies two independent pixel fails (pixels that differ by more than 15% from pixel average of neighbors) that form a couplet with 2 minor pixel fails within the inner area, the device fails the test and is rejected. If however the test identifies 2 couplets where the pixels span the border between the inner and outer areas and where only one of the pixels in the inner area is determined as a major fail and the other a minor fail, then this device passes the test.
8.4.4
Cluster definition
We define a cluster fail as a failing pixel with at least two adjacent failing pixels. In the example from Figure 34, there are additional pixel fails in positions [0] and [7]. This example constitutes a cluster. A sensor containing a cluster is always rejected. Figure 34: Cluster example
[X] [X] [6] [1] X [5] [2] [3] [4]
8.5
Summary pass criteria
Table 25: Sensor pixel defect pass criteria
Single pixel fails <=120 Minor Coupleta 1 (2) Major Coupletb 0 Clusters 0
a. Test program will allow maximum of one minor couplet in inner zone of pixel array. Test program will allow maximum of two minor couplets in outer zone of pixel array. b. No major couplet allowed.
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VV6501
Defect Categorisation
8.6
Physical aberrations
Silicon surface irregularities and external marks, both pits and deposits, on the package glass lids can cause a deterioration in image quality. STMicroelectronics recognize that this could compromise the product quality and therefore have introduced a specific test algorithm to identify and reject samples that display these phenomena. The pass/fail criteria for this test are given in Section 8.6.1.
8.6.1
Test details
Figure 35: Test area definition
The test defines 2 areas:
q
A small area: 9 by 9 pixels with pixel under test at the centre of this area (shaded blue in Figure 35) A large region, 31 by 31 pixels (shaded red in Figure 35)
q
An average value is calculated for both the `small' and `large' areas.The areas then scan across the whole array so that every pixel is evaluated. Due to the nature of the test, only the red pixels are used. The next stage of the test is the creation of a pixel map with the coordinates of the failing pixels. A pixel location is identified as a fail in the map if it satisfies the criteria outlined in Table 26 below.
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Defect Categorisation
Table 26: Criteria for pixel to be entered in failure map
Pixel location is a fail in map if Small average < Large average - (1.2% of Large average) or Small average > Large average + (1.2% of Large average)
VV6501
The contents of the fail map determine whether the sensor fails the physical aberration test. The fail criteria are given in Table 27 below: Table 27: Physical aberration test fail criteria
Fail physical aberration test if > 82 contiguousa pixel entries in the failure map a. An example of contiguous pixels entries is given in Figure 36
Figure 36: Contiguous pixels example
The group of pixels enclosed in the circle are contiguous, that is every pixel in the group is attached to at least one neighboring pixel.
The other pixel entries shown in the figure are non contiguous as they have no touching neighbors.
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9 Package Mechanical Data
VV6501
A +0.20 10.67 - 0.13 No 1 No 36 0.55 0.05 B D No 36 No1 C [36x] 0.89 0.15 (R0.15) [36x]
(R0.30) [4X]
(R0.30) [4X] 7.37 0.13 8.64 0.13
No. 1 index ( 0.51)
0.08 [AT S/R] Note 2 A 0.08 A 0.08 (R 0.15) [x 4] 1.016 0.08 8.128 0.13 [P = 1.016 x 8]
Notes: 1. Gold plate 0.3 m minimum over 1.27 ~ 8.89 m nickel 2. Seal area and die attach area shall not be without metallization 3. All tolerances are 0.13 unless otherwise specified
Option K A B C D 1.549 0.161 0.571 0.05 0.546 0.05 0.432 0.05
[4 0. x] 51
[36 x] 0.51 0.08
Option N 1.54 0.16 (0.62) 0.51 0.05 0.41 0.03
1.910.15
Package Mechanical Data
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Design-In Information
VV6501
10
10.1
Design-In Information
Basic support circuit
Figure 37 : Basic support circuit
10uF 1V8 5V0 PDVREG1V8 3V3
10uF
6.8nF
2.2uF
A suitable choice for the bipolar transistor would be a ZTX749. It satisfies the technical specification and is very cost effective.
5 6 PORB 3V3 SUSPEND 8 9 7
4
3
2
1
36
35
34
33 32 31 n/c n/c
Video
VV6501
30 29 28 27 2K2 26 25 24 AUDOUTN AUDREF 100nF AUDOUTP 470nF 2.2uF
100nF
1uF
11 4K7 SDA SCL 4K7 13 CLKIN 14 15 16 17 18 19 20 12
Digital
21
Audio
22 D3 D2
10
23
FST
D1
STMicroelectronics advises the use of a grounding star point. All decoupling capacitors should be placed as close to sensor as possible. The support circuit outlined above describes a USB based system with a nominal 5V supplying the device.
10.2
Transistor choice
The ZTX749 has a high min. HFE (lower on-chip current). It is also inexpensive and has good heat dissipation.
10.3
Pin 1 and image orientation
Please note that for the sensor array to produce a correctly aligned image, pin 1 should be located at the `top' rather than 180 degrees rotated at the `bottom' (see Figure 3).
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QCLK
D0
D4
VV6501
Evaluation Kits
11
Evaluation Kits
Evaluation kits are available to demonstrate the VV6501 sensor technology. The sensor can be demonstrated using the PCI card based standard evaluation kit STV-EVK-E01. A daughter card kit is also available to purchase separately. The daughter card is a simple pcb on which the sensor is mounted. The daughter card can then be plugged into the main evaluation kit pcb. The evaluation kit is supplied with supporting software that enables the customer to program the sensor via an I2C interface. Table 28: Ordering details
Part Number STV-EVK-E01 STV-6501CD01 Description Sensor only evaluation kit for VV6501C001 Sensor daughter card for VV6501C001
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VV6501
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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